Agenda

PAISE 2026 will be held on Tuesday, May 26, 2026, in the Bacchus Room at the Marriott on Canal Street in New Orleans, Louisiana, USA.

Keynote: AI/ML Infrastructure: Accelerating & Scaling for the Future

Abstract: In this talk, I will cover AI/ML infrastructure advancements for the current and future growth of AI workloads and use cases. I will touch upon the journey of developing TPUs, describe the high level architecture of the Ironwood TPU and discuss the benefits of scaling compute, memory and communications for large-scale AI/ML infrastructure. I will also touch upon the emerging growth in AI use cases (e.g. agentic workloads) and the associated opportunities and challenges for continuing to accelerate & scale the infrastructure for future needs.

Ravi Iyer is a Principal Engineer in Google’s AI and Infrastructure group. Before joining Google, he was an Intel Fellow and Sr. Director of the Emerging Systems Lab at Intel Labs. Ravi has published more than 150 papers spanning topics related to edge/cloud infrastructure, AI/ML accelerators, server architecture and SoCs, domain-specific co-design, network acceleration, workload characterization, and performance analysis. Ravi has been granted more than 50 patents, with many additional patents pending. Ravi earned his Ph.D. in Computer Science from Texas A&M University. He is also an IEEE Fellow.

Panelists: The Future of AI@Edge

Samira Afzal, Baylor University

Samira Afzal is a Postdoctoral Research Associate at Baylor University with five years of post-Ph.D. experience in multimedia systems, multipath video streaming, and AI-driven sustainable video workload management across cloud and edge infrastructures. She was a Ph.D. researcher at Samsung Brazil and has contributed to international research collaborations with Bitmovin and TNO. Her work has resulted in peer-reviewed publications, publicly released datasets, an open-source tool for monitoring video encoding resource usage, contributions to MPEG/ISO standardization for enhancing the MPEG Media Transport protocol, and patented techniques for multipath video delivery. Her research has supported the development of sustainable video streaming platforms recognized with international innovation awards.

Ali Jannesari, Iowa State University

Ali Jannesari is an Associate Professor and Director of the Laboratory for Software Analytics and Pervasive Parallelism in the Department of Computer Science at Iowa State University (ISU). His research focuses on the intersection of High-Performance Computing (HPC) and Artificial Intelligence (AI). Dr. Jannesari has published over a hundred refereed articles, several of which have received awards. His research has been funded by both U.S. and European agencies, including the National Science Foundation (NSF), the Department of Energy (DOE), the German Research Foundation (DFG), the Federal Ministry of Education and Research (BMBF), and the German Academic Exchange Service (DAAD). Prior to joining ISU, he was a Senior Research Fellow at the University of California, Berkeley. During his time in Germany, he led the Multicore Programming Group at the Technical University of Darmstadt and served as a junior research group leader at RWTH Aachen University. He also worked as a Postdoctoral Research Fellow at the Karlsruhe Institute of Technology (KIT). Dr. Jannesari holds a Habilitation from the Technical University of Darmstadt and earned his Ph.D. in Computer Science from the Karlsruhe Institute of Technology.

Elaheh Sadredini, University of California, Riverside

Elaheh Sadredini is an Assistant Professor in the Department of Computer Science at the University of California, Riverside, with a cooperating appointment in Electrical and Computer Engineering. Her research develops secure, high-performance, and energy-efficient data-centric architectures, with a particular focus on memory-centric and in-SRAM computing that spans the continuum from Internet of Things devices to the cloud — work recognized by the NSF CAREER Award for “Enabling Memory-Centric Computing from Internet of Things to Cloud.” Her contributions have appeared in top-tier venues including MICRO, ISCA, ASPLOS, HPCA, USENIX Security, DAC, ICS, and KDD, and have led to multiple patents and several Best Paper recognitions. She serves as Area Chair for ISCA 2026 and co-general chair for IISWC 2025. She earned her Ph.D. in Computer Science from the University of Virginia in 2019.

Marco D. Santambrogio, Politecnico di Milano

Marco D. Santambrogio is a Full Professor at Politecnico di Milano, and an Adjunct Professor del College of Engineering of the University of Illinois at Chicago (UIC) since 2009. He was Research Affiliate with the Computer Science and Artificial Intelligence Laboratory (CSAIL) at Massachusetts Institute of Technology (MIT) from 2010 to 2015. He received his laurea (M.Sc. equivalent) degree in Computer Engineering from the Politecnico di Milano (2004), a M.Sc. degree in Computer Science from the University of Illinois at Chicago (UIC) in 2005 and his PhD degree in Computer Engineering from the Politecnico di Milano (2008). He founded the Novel, Emerging Computing System Technologies Laboratory (NECST Laboratory), merging together the two previously existing labs: MicroLab and VPLab, and he is, since then, the Director of the NECSTLab. He conducts research and teaches in the areas of reconfigurable computing, self-aware and autonomic systems, hardware/software co-design, embedded systems, and high performance processors and systems. Marco D. Santambrogio is a senior member of both the IEEE and ACM, and he has been the IEEE Italy Computer Society Chair from 2019 to 2025.

Thejasvi Vijayaraj, Google LLC

Thejasvi Vijayaraj leads performance and co-design efforts for Google’s large-scale AI infrastructure. He specializes in hardware/software co-design, focusing on Large Language Models (LLMs) and recommendation models. His work is targeted at optimizing performance and power efficiency for a wide range of production workloads across several generations of Google Tensor Processing Units (TPUs). This work has informed the development of the TPU roadmap and helped align the Gemini architecture with specific hardware features to improve overall efficiency. Thejasvi also addresses scaling challenges for training and inference systems by identifying and mitigating chip and system bottlenecks, influencing network topologies, and optimizing workload mapping strategies. Prior to Google, Thejasvi worked on SoC and platform architecture at Apple and Rivos. He developed his foundational interest in parallel and distributed computing during graduate studies at Georgia Tech.